In testing semiconductor integrated circuits by a semiconductor test system, the semiconductor IC device to be tested (device under test) is provided with test signals and the resultant output signals of the device under test are compared with expected value signals prepared in advance to determine whether the intended functions of the integrated circuit under test is performed correctly. Because the recent semiconductor integrated circuits become more and more complicated and high level, the size of the test signals to test such semiconductor integrated circuits must be increased accordingly. Further, to fully evaluate such an integrated circuit, the test signal of high timing resolution must be applied to the device under test. Such timings of the test signal is produced by a timing signal generation circuit.
As noted above, the timing resolution of the test signals used by the semiconductor test system must be very high. In fact, the test signals are usually required to have timing resolution higher than the time period of a reference (system) clock in the semiconductor test system. For example, while a time period of the reference clock used in a semiconductor test system is 10 ns (nanosecond), the timing resolution of the test signals is required to be 0.3 ns or higher. Therefore, the timing generation circuit is configured by a combination of a coarse delay control unit a fine delay control unit. The coarse delay control unit is to produce timings which are integer multiple of one cycle of the reference clock and the fine delay control unit is to produce timings which are substantially smaller than the one cycle of the reference clock signal.
An example of conventional timing generation circuit is shown in FIG. 1. The upper part of FIG. 1 is a coarse delay control unit which produces a timing of an integer multiple of the reference clock cycle. The lower part of FIG. 1 is a fine delay control circuit which produces a timing substantially smaller than one cycle of the reference clock. In the example of FIG. 1, the coarse delay control unit is formed of a counter 11, a register 12, a comparator 13, a flip-flop 14 and an AND gate 16.
In the coarse delay control unit, the counter 11 is reset by a tester rate signal and the coarse delay data is loaded in the register 12. The counter 11 counts the reference clock. The counted data of the counter 11 is compared with the coarse delay data stored in the register 12 by the comparator 13. When both data match with one another, the comparator 13 produces a coincidence signal which is re-timed by the flip-flop 14 and the AND gate 16. Thus, the output of the AND gate 16 shows a delay time which is an integer multiple of the reference clock cycle. The delayed output signal from the AND gate 16 is provided with a delay time which is smaller than the reference clock cycle by the fine delay control unit.
The fine delay control unit is configured by a plurality of delay circuits for producing weighted small delay times. In the example of FIG. 1, the fine delay control unit includes a delay circuit 17 for generating a delay time equal to a 1/2 cycle of the reference clock and a delay circuit 18 for generating a delay time equal to a 1/4 cycle of the reference clock. The delay circuit 17 is formed of AND gates 21 and 22, a delay element 23, and an OR gate 24. Similarly, the delay circuit 18 is formed of AND gates 25 and 26, a delay element 27, and an OR gate 28.
The delay elements 23 and 27 respectively produce the above noted delay times which are 1/2 cycle and 1/4 cycle, respectively, of the reference clock. As shown in the circuit configuration of FIG. 1, by the fine timing data provided to the AND gates, it is determine as to whether or not the input signal to the delay circuit is introduced to the signal path having the delay element for adding the delay time. As a consequence, at the output of the timing generation circuit of FIG. 1, a timing signal having a high timing resolution is produced. In an actual application to a semiconductor test system, a large number of such delay circuits are employed to produce a fine delay time having timing resolution of, for example, 1/32 cycle of the reference clock.
Because the semiconductor test system is a very large scale electric equipment, a large portion of the inner electric circuits are configured by CMOS semiconductor integrated circuits for keeping the cost and power consumption low. Thus, the timing signal generation circuit of FIG. 1 is usually formed as a part of a large scale CMOS integrated circuit. For example, other components of the semiconductor test system, such as driver waveform control circuits and logic comparators, are also formed in the same CMOS semiconductor integrated circuit having the timing signal generation circuit. Consequently, the operation frequency of the timing signal generation circuit is limited to the operation speed of the CMOS integrated circuit. As is known in the art, although the operation speed of CMOS integrated circuits is high compared with other MOS type integrated circuits, the operation speed is lower than that of a bipolar integrated circuit or a gallium arsenide integrated circuit.
Further, in the foregoing fine delay circuit, each delay element is formed of a plurality of CMOS transistors or CMOS gate circuits. Since the operation speed of the CMOS intergrated circuit is not very high as noted above, the reference clock frequency to be used in the timing signal generation circuit cannot be very high, resulting in using the reference clock having a relatively large clock period. Therefore, the delay time assigned to the delay element (such as 1/2 period or 1/4 period of the reference clock) must also be large. For producing such a relatively large delay time, a large number of CMOS gate circuits must be series connected to form the delay element. Accordingly, the delay time produced by such a delay element tends to be subject to voltage changes or temperature changes, resulting in the timing instability. Thus, the conventional timing generation circuit has a drawback in which the timing resolution cannot be sufficiently increased.